The Space Research Institute in Graz invites applications for a
(Senior) Engineer (f/m/x) for FPGA development and validation
(Full-time employee)
The IWF is looking for a talented and experienced candidate interested in developing and testing scientific instrumentation for space missions to join its on-board computing group. The on-board computing group has provided several instrumental contributions to international space missions. EBOX&DPU on ESA/CAS’ SMILE, the RDCU on ESA’s PLATO, PICAM on ESA/JAXA’s BepiColombo, ASPOC on NASA’s MMS etc. The group is currently developing the data processing unit (DPU) onboard ESA Comet Interceptor and ATHENA missions, and is also involved in the ESA’s ARRAKIHS mission for which the electronic box (EBOX) and the common data processing units (CDPUs) will be developed. In addition, the group is engaged in a number of internal R&D activities, such as custom interfaces for optical & near-infrared sensors and integration of machine-learning architecture on FPGA for compression and event detection. We are looking for an FPGA engineer to support the firmware development of its hardware contribution to ESA missions as well as supporting the R&D activities.
Your Tasks
- Define the requirement specification and design as well as perform the implementation & testing of the firmware application developed by the research group.
- Support unit level testing (e.g., functional tests for DPUs) and contribute to the respective test reports.
- Support the development of R&D projects for the group.
Your Profile
- Master degree, Doctorate degree or Engineering diploma in electrical, computer science or aerospace engineering, with an interest in space instrumentation.
- Experience in developing FPGA firmware, preferably for space applications including the knowledge of the relevant standards.
- Knowledge of the VHDL hardware description language, verification methodology and implementation steps.
- Knowledge of programming languages such as C, C++ or Python, particularly for developing test scripts and execution applications.
- Experience in electrical design and in using laboratory equipment for testing electronics will be an asset.
- Proficiency in English.
Our Offer
The appointment begins as early as 1 June 2025 for initially 2 years, with option for renewal afterwards. We offer an annual gross salary of € 51.930,76) for a junior level position according to the collective agreement of the Austrian Academy of Sciences (grade N4/1). Depending on qualification and senior experience, the salary can be negotiated (up to N5/1).
Applications must include a cover letter in addition to (1) curriculum vitae, (2) cover/motivation letter and (3) certificates for full academic record. Please send the application as one PDF file (Job ID: IWF 054TEC225) to gabriel.giono @oeaw.ac.at no later than May 30, 2025. Inquiries about the position should be directed to Gabriel Giono.
The Austrian Academy of Sciences (OeAW) pursues a non-discriminatory employment policy and values equal opportunities, as well as diversity. Individuals from underrepresented groups are particularly encouraged to apply.
